View SAF82520-N_7809153.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

semiconductor group 5 03.94 sab 82520, a high-level serial communications controller (hscc), has been designed to free the user from tasks occurring in communication via networks and trunk lines. sab 82520 is an x.25 lapb/lapd controller which, to a large degree performs communications procedures independently of cpu support. a parallel processor bus constitutes the m c system. the communications interface is implemented by two full-duplex hdlc channels, which can be operated independently from one another. the hscc is connected to the transmission line via additional line drivers or modems. external logic is cost-effective because clock recovery can be performed by an on- chip oscillator, dpll circuits and a programmable baudrate generator. type ordering code package sab 82520-n q67100-h8400 p-lcc-28 (smd ) sab 82520-p q67100-h8014 p-dip-28 saf 82520-n q67100-h8610 p-lcc-28 (smd) saf 82520-p q67100-h8512 p-dip-28 high-level serial sab 82520 communications controller (hscc) saf 82520 1 features two independent hdlc channels implementation of x.25 lapb/lapd protocol programmable timeout and retry conditions fifo buffers for efficient transfer of data packets digital phase-locked loop for each channel baudrate generator and oscillator different modes for clock recovery and data encoding high-speed data rate (up to 4 mhz) supports bus configuration by collision resolution telecom-specific features programmable 8-bit parallel m p interface advanced cmos technology low power consumption; active: 25 mw at 4 mhz standby: 3 mw sab 82520: operating temperature 0 to 70 ?c saf 82520: operating temperature ?40 to 85 ?c
sab 82520 saf 82520 semiconductor group 6 figure 1 logic symbol
sab 82520 saf 82520 semiconductor group 7 pin configurations (top view) figure 2 p-dip p-lcc
sab 82520 saf 82520 semiconductor group 8 25 26 27 28 1 2 3 4 r da r db i /o i/o i /o i /o i /o i /o i /o i /o address data bus the multiplexed address data bus transfers data and commands between the m p system and the hscc. 5 12 o o rtsa rtsb request to send when the rts bit in mode is set, the rts signal goes low. when the rts bit is reset, the signal goes high of the transmitter has finished and there is no further request for a transmission. in a bus configuration, rts goes low during the actual transmission of a frame shifted by a clock period, excluding collision bits. 6 11 i i ctsa /c da ctsa /c da clear to send /collision data a low on the inputs enables the respective transmitter. if the transmitters are always enabled, cts should be connected to vss. in a bus configuration the external serial bus must be connected to the respective c ?d pin. 7 10 i i receive data these lines receive serial data at standard ttl or cmos levels. t da t db 8 9 o o transmit data these lines transmit serial data at standard ttl or cmos levels. they can be programmed as push-pull or open-drain outputs. res 13 i reset a high on this input forces the hscc into reset state. the hscc is in power-up mode during reset and in power-down mode after reset. the minimum pulse length is 1.8 m s. ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 1.1 pin definitions and functions pin no. symbol input ( i ) output (o) functions v ss 14 ground (0 v) int 15 o interrupt request the signal is activated when the hscc requests an interrupt. it is an open-drain output.
sab 82520 saf 82520 semiconductor group 9 pin definitions and functions (cont?) pin no. symbol input (i) output (o) functions ale 16 i address latch enable a high on this line indicates an address on the external address data bus, selecting one of the hscc internal sources or destinations. cs 17 i chip select a low on this signal selects the hscc for a read/write operation. 18 19 i /o i /o transmit clock these pins can be programmed in several different modes of operation. t clk may supply the transmit clock for the respective channel, a receive strobe signal (t clk a) and a transmit strobe signal (t clk b) or a frame synchronization signal (t clk a, clock mode 5). programmed as outputs, t clk supply the transmit clock of the respective channel or a tristate control signal, indicating the programmed transmit time slot (t clk b, clock mode 5). t clk b t clk a 20 21 i i receive clock these pins can be programmed in several different modes of operation. in each channel r clk may supply the receive clock, the receive and transmit clock, the clock for the baud rate generator or the clock for the dpll. they also can be programmed for use as a crystal oscillator. r clk b r clk a v dd 22 power + 5 v power supply. wr 23 i write this signal indicates a write operation. rd 24 i read this signal indicates a read operation.
sab 82520 saf 82520 semiconductor group 10 1.2 functional description in a point-to-multipoint or in a multimaster configuration the hscc can be used as a central station (master) or a peripheral station. as a peripheral station the hscc can initiate the transmission of data. an internal function block provides for collision avoidance, which may occur if several stations start the transmitting simultaneously. furthermore, in a special operating mode the hscc can transmit or receive data packets in programmable time slots; this makes sab 82520 especially suitable for applications in systems designed for packet switching. in this application in particular, the integrated collision- resolution mechanism provides optimal utilization of system-internal pcm paths. a number of characteristics which distinguish the sab 82520 from conventional low-level hdlc devices are described below. support of layer-2 functions by hscc "low-level" hdlc devices usually support various of protocols. when applying the hdlc protocol mainly bit-oriented functions such as bit stuffing, crc check, flag and address recognition are performed. sab 82520 has been especially designed to support the iso hdlc protocol. in addition to the bit-oriented functions, the device provides a high degree of procedural support and evaluates the layer-2 control field. the communications procedures are processed between the communications controllers and not between the processors. as a result procedure handshaking is no longer necessary. the processor is informed of the status of the procedure, however. the dynamic load of the processor is thus largely reduced. to maintain cost effectiveness and flexibility, not all layer-2 functions have been implemented as hardware. instead, functions such as connection set-up/connection clear-down and error recovery in case of protocol errors are performed by the processor software. operating modes the distribution of functions between hscc and cpu applies to the auto mode. as a prerequisite for this operating mode, the window size between transmitted and acknowledged frames has to be limited to 1 frame. alternatively, transparent modes can be applied, the data field as well as the layer-2 headers are forwarded directly to the cpu. the reception and transmission of messages is fully controlled by the cpu. this operating mode is selected when the component is used as a central station (master) or if the accepted distance between transmitted and received frames (window size) is larger than 1 frame. furthermore, there is a possibility to bypass the receiver and to get access to the received data directly. fifo buffers for efficient transfer of data packets another feature of the sab 82520 can be seen in the buffers that are used for temporary storage of data packets which are transferred between the serial communication interface and the parallel system bus. due to the overlapping input/output operation (dual-port behavior), the maximum length of the data packets is not limited by the buffer size. the dynamic load of the processor is reduced by transferring the data packets block by block.
sab 82520 saf 82520 semiconductor group 11 serial interface the serial interface provides two independent, high-performance communication interfaces. as already mentioned, the iso hdlc layer-2 protocol is supported by the hscc. in addition, layer-1 functions are provided by means of on-chip circuits. eight different operating modes can be selected to clock the serial data stream. during the self-clocked operating mode, the transfer clock is recovered from the received data stream by means of an external crystal only. on-chip oscillator and dpll circuits sample the received bit stream and adjust the clock edge to the center of the data bit. the bit stream is synchronized in the externally clocked operation mode by external clock signals. on the whole, 4 different clock signals separated by direction and channel, can be forwarded. in addition to the data clock, an externally supplied strobe signal can be applied to determine the time period during which data is to be received or transmitted. using another operating mode, a time slot (up to 64 bit) can be programmed for transmitting data and another time slot for receiving data. one time slot consists of eight clock cycles. with the point-to-multipoint configuration, comprising a central station (master) and several peripheral stations (slaves), data transmission can be initiated by a slave. if several stations (slaves) transmit data simultaneously, the bus is assigned to one station by a collision- resolution procedure implemented by the hscc. the maximum data rate of the externally clocked operating mode is 4 mbits per second. in the self-clocked operating mode with an external reference clock or the crystal oscillator, the maximum clock rate is 11.52 mhz, the maximum data rate will be 1220 kbit/s. one fifo buffer with a total capacity of 64 bytes per direction and channel is divided into two memory pools of 32 bytes each. when a pool is filled (receive mode) or emptied (transmit mode) via the serial interface, the processor is prompted by interrupt to read or write this pool. subsequently the second pool is filled or emptied. during this time the cpu can transfer the first block thereby ensuring availability of the pool. with a serial transfer rate of 1 mbit/s the reaction time between the first prompting and data overflow with loss of data is 256 m s. in addition, the transmit fifo provides the flexibility for temporarily storing blocks of various lengths, which can be received in rapid succession. the fifo will also store a data packet when a preceding short data packet stored in the memory has not yet been read by the processor. the hscc is especially suitable for cost-critical applications with single chip processors due to its memory organization and on-chip memory control. move string commands are available for high-performance applications where fast data rates at the communication interface and a high level of processor performance are required. the fifo can then be addressed by the automatically incremented address.
sab 82520 saf 82520 semiconductor group 12 applications figure 3a point-to- point configuration figure 3b point-to- multipoint configuration figure 3c multimaster configuration
sab 82520 saf 82520 semiconductor group 13 description of block diagram the chip contains a serial interface for two channels, including a dpll and collision-detection block, a data-link controller and the fifo buffers. the m p interface, including the status and command registers, is used for both channels. these functions are implemented in 2 m m cmos technology. figure 4 block diagram
sab 82520 saf 82520 semiconductor group 14 2 operating modes the m c sets the operating modes as well as controlling the functional sequences by reading or writing special registers in the hscc. a detailed description of these registers has been provided under item 5. the following functions are performed in accordance with the above: setting of operating modes transfer of data packets layer-2 functions test loops bus mode dpll mode baud rate generator the processor is informed by interrupt of special events in the hscc. the int output has been designed as an open-drain output, providing the possibility of connecting several hscc? to an interrupt input of the m c. subsequent to an interrupt, the interrupt status register/channel b (ista) must be read. five interrupt events can be read out directly. bit 0 indicates the extended interrupt register/channel b (exir), bit 1 the exir/channel a and bit 2 the ista/channel a. indications, which do not trigger an interrupt, can be read for each channel from the respective status register (star). command and acknowledgements from the m c are forwarded to the hscc by writing to the command register (cmdr). the clock multiplexer? operating mode as well as the configuration of the serial interface can set in the common configuration register (ccr), while the operating mode of the hdlc controller for each channel can be individually set in the mode register. 2.1 the hdlc controller? operating modes the different operating modes differ in the treatment of the hdlc frames. there are 5 operating modes which can be set with software. auto mode non-auto mode transparent mode extended transparent mode 0 extended transparent mode 1 the type of processing of the layer-2 header of hdlc frames differs according to the operating mode. auto mode characteristics: window size 1, random message length, address recognition. the component autonomously processes all numbered frames (s + i frames) of an lap. all unnumbered frames on this lap as well as all frames on logical connections operating in parallel are forwarded directly to the m c.
sab 82520 saf 82520 semiconductor group 15 data in the i field of the frames are temporarily stored in the rfifo. the hdlc control field as well as additional information can be read from special registers. according to the selected programming mode, the hscc can perform a two byte or one byte address recognition. the higher ranking address byte of a two byte address will be compared with the fixed value fe h and/or fc h as well as two bit 1 will thereby be excluded from the address comparison and is instead interpreted as a command/response bit, depending on the programming of the rah1 register (cri bit). similarly, two comparison values can be entered into special registers (ral1, ral2) for the lower ranking address byte. a valid address will be recognized in the case where the higher ranking and lower ranking address bytes correspond to one of the comparison values. thus, the hscc can be called with a maximum of six address combinations, however, only the lap identified through the address combination rah1, ral1 will be processed in the auto mode. in case of a one byte address, ral1 and ral2 will be used as comparison registers. according to lap b, the value in ral1 will be interpreted as command and the value in ral2 as response. note: in case of a one-byte address the value of rah1 must be set to 00 h . non-auto mode characteristics: address recognition, random window size. all frames with a valid address comparison are forwarded directly to the m c. up to 64 data bytes or two complete frames can be temporarily stored in the hscc. data in the i field is temporarily stored in the rfifo. the hdlc control field and additional information can be read from special registers. transparent mode characteristics: address recognition high byte. only the higher address byte in a two byte address will be compared. data in the i field is stored temporarily in the rfifo. the second address byte can be read from the receive address byte low register 1 (ral1), while the hdlc control field can be read from the receive hdlc control register (rhcr) and additional information from the receive status register (rsta). since the address compare procedure is omitted for one byte address, each frame will be stored. extended transparent mode 0 characteristics: no address recognition. the entire frame between the start flag and the first crc byte is stored in the rfifio. in addition, the first byte after the start flag can be read from the ral1, the second byte from the rhcr, and additional information from the rsta.
sab 82520 saf 82520 semiconductor group 16 extended transparent mode 1 characteristics: full transparency, hdlc receiver deactivated. with the receiver deactivated (mode register), received data bytes can be read from ral1. the hdlc receiver is in this case by-passed. data will be updated in ral1 after eight clock periods. characteristics: address recognition high byte, hdlc receiver active. the first byte after the opening flag is compared with fe h , fc h as well as with the values programmed in rah1 and rah2. in the case of a match, the remaining bytes of the frame (up to but excluding the crc dependence) are stored in the rfifo. figure 5 internal processing of an hdlc frame figure 6 internal address compare
sab 82520 saf 82520 semiconductor group 17 figure 7 hscc clock sources 2.2 operating modes of the clock multiplexer the hscc includes an internal oscillator circuit, a baud rate generator as well as two digital dpll?. the receive and transmit clock for each channel can be generated separately and/or supplied externally. the component clock, on the other hand, is derived from the transmit clocks for channel a and/or channel b, eliminating the need for additional clock sources. during certain operating modes, a separate receive and transmit strobe can be supplied. the possible clocking sources are: for the receive clock r clk a/r clk b-pin dpll channel a/b oscillator for the transmit clock r clk a/r clk b-pin t clk a/t clk b-pin dpll channel a/b baud rate generator frequency divided by 16 oscillator note: the ratio between the receive frequency ( f r ) and the transmit frequency ( f x ) for a channel must satisfy the condition f r / f x < 2.8; there are no restrictions on the phase shift. slower transmit data rates can be realized with receive and transmit strobe.
sab 82520 saf 82520 semiconductor group 18 pins r clk a/r clk b and t clk a/t clk b generate the clock for the hscc. r clk a/r clk b is used as crystal connection for the internal oscillator circuitry or as clock input. depending on the programming of the timing control register (tcr), t clk a/t clk b can be used either as a clock input or clock output. the clock sources for the transmitter, receiver and baud rate generator as well as the sources for the receive and transmit strobe as a function of the operating mode selected in the common configuration register (ccr) and in the timing control register (tcr) are shown in table 1. the clocking source for the dpll? is always the internal baud rate generator; the scaling factor (divider) of the baud rate generator can be programmed through the timing control register (tcr) and baud rate generator register (bgr) between 1 and 2048. in power-down mode, all internal clocks as well as the oscillator circuitry are disabled. after a hardware reset, the hscc will be in the power-down mode. clock mode 0 separate, externally generated receive and transmit clocks are forwarded for each channel to the hscc via their respective pins. clock mode 1 externally generated, but identical, receive and transmit clocks are forwarded for each channel via pins r clk a/r clk b. in addition, a transmit strobe can be connected via t clk b or a receive strobe via t clk a. this operating mode can be applied for transmission in the time division multiplex method or for adjusting disparate transmit and receive data rates. clock mode 2 the baud rate generator is driven with an external clock (r clk a) and it delivers a reference clock for both dpll?, which in turn generate the receive clock for the corresponding channels. depending on the programming of the timing control register (tcr), the transmit clock will be either an external clock signal (pins t clk a/t clk b) or the clock delivered by the baud rate generator divided by 16. in this case the transmit clock can be outputted via t clk a/t clk b. clock mode 3 baud rate generator and dpll? are operated with an external reference clock (r clk a) and provide the receive and transmit clock for the respective channel. this clock can also be supplied via t clk a/t clk b. clock mode 4 the transmit and receive clock for both channels is directly supplied by the on-chip oscillator. in addition, this clock can be supplied via t clk a and t clk b.
sab 82520 saf 82520 semiconductor group 19 table 1 clock mode and clock sources 1) t x clka is used for synchronization, t x clkb supplies a tristate control signal (cf. 4.1.2.6) clock mode tcr common clock sources channel a clock sources channel b clock sources common sources clock output tss tio brg dplla/b rec trm rec trm r strobe x strobe t x clka/b 0 1 2 2 3 4 5 6 6 7 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 1 r x clka r x clka r x clka osc osc osc brg brg brg brg brg brg r x clka r x clka dplla dplla dplla osc r x clka dplla dplla dplla t x clka r x clka t x clka brg:16 dplla osc r x clka t x clka brg :16 dplla r x clkb r x clkb dpllb dpllb dpllb osc r x clkb dpllb dpllb dpllb t x clkb r x clkb t x clkb brg:16 dpllb osc r x clkb t x clkb brg:16 dpllb t x clka tsar t x clkb tsax brg:16 dplla/b osc 1) brg:16 dplla/b
sab 82520 saf 82520 semiconductor group 20 clock mode 5 this operating mode has been designed for application in time slot oriented pcm systems. the receive and transmit clock is identical for each channel and must be supplied externally via r clk a/ r clk b pins. the hscc receives and transmits during certain 8-bit time slots in each frame. the transmit time slot is additionally indicated by a tristate control signal via t clk b, whose output is set to log 0 during the transmit period. the receive time slot may be programmed via timeslot assignment register receive, tsar (resp. transmit, tsax). a frame synchronization signal is delivered to the hscc via t clk a. the clock shift of the transmit time slot with respect to the synchronization signal may be programmed using tsar/ tsax (bits tcs2-0), while the clock shift for the receive time slot is programmed using the timing control register (tcr, bit rcs2-0). the location of the transmit and receive time slots as a function of their programming and the clock shift is shown in figure 8a; 8b; 8c. figure 8 position of receive time slots
sab 82520 saf 82520 semiconductor group 21 figure 9 position of transmit time slots timing mode 1 if the component is used in systems operating with a number of time slots other than 64 or 32, the frame synchronization signal must be supplied for each frame start-up. also, in this case, the time slot 0 can be used only if the clock shift equals 0 (tcs2-0 resp. rcs2-0 equal to 7). it is possible to transmit/receive either 64 kbit or 56 kbit channels, the selection being made in tcr (bit ccs). when receiving a 56 kbit channel only, the first seven bits of a time slot will be valid. for transmitting a 56 kbit channel, the first seven bits are used for data, the last bit being set to one.
sab 82520 saf 82520 semiconductor group 22 figure 10 position of transmit time slots timing mode 2 figure 11 transmission of 56 kbit channels bus mode
sab 82520 saf 82520 semiconductor group 23 clock mode 6 baud rate generator and the dpll? are operated with the reference clock provided by the on- chip oscillator and supply the receive clock for the respective channel. the transmit clock is taken to be either the externally provided clocking signal (t clk a/t clk b) or the baud rate generator frequency divided by 16. the transmit clock may also be made available as an output (t clk a/t clk b). clock mode 7 baud rate generator and the dpll? are operated with the reference clock provided by the on- chip oscillator and supply the transmit and receive clock for the respective channel. this clock can be also supplied via t clk a/t clk b. 2.3 configuration of the serial ports in addition to the clock pins, the serial interfaces of the hscc include the data inputs (r da/r db) and the data outputs (t da/t db) as well as the pins for the modem control or the bus access control (rtsa/rtsb , ctsa/ctsb ). the data outputs can be operated as driver or as open drain outputs. during the idle state, either the idle code (log 1) or flags are outputted via t da/t db. these settings as well as the selection of the operating mode of serial interfaces can be performed in the common configuration register (ccr). a transition on the cts input will, with a corresponding programming of the timing control register (tcr), generate an interrupt (exir). the actual value can subsequently be sent from star point-to-point, nrz encoding the hscc transmits and receives data in the nrz format. figure 12 nrz encoding
sab 82520 saf 82520 semiconductor group 24 data output is performed with the rising clock edge, data input with the falling clock edge. a transmit request will be indicated by outputting log 0 at the request-to-send output (rtsa/ rtsb ). it is also possible to program the rts outputs by software. after having received the permission to transmit (ctsa/ctsb ) the hscc transmits a frame. figure 13 rts ?ts handshaking in the case where permission to transmit is withdrawn during the transmission process, the frame is aborted (idle). after a new permission to transmit has been received and if all of the data are still available in the hscc, the terminated frame will be re-transmitted (self-recovery), without interrupting the cpu. however, if the permission to transmit is withdrawn after the 32nd byte in the information field, the transmitter and the xfifo are reset, the rts output is deactivated and an interrupt is generated for the m c. note: in the case where permission to transmit is not required, the ctsa /ctsb inputs can be connected directly to v ss . point-to-point, nrzi encoding the hscc transmits and receives data in the nrzi format. figure 14 nrzi encoding during nrzi encoding, level changes are interpreted as log 0, and no changes in level as log 1. since no more than 5 successive log 1? can appear in an hdlc frame, this type of encoding is especially suitable for data transfer with an asynchronous clock (dpll operating mode). the utilization of modem control signals corresponds to nrz encoding ( figure 12 ).
sab 82520 saf 82520 semiconductor group 25 bus configuration, timing mode 1 in this bus configuration, the nrz encoding and a logic wired or connection of the individual transmitters are required. data is outputted with the rising clock edge via t da/t db. the external bus is connected to the c da/c db input, data is clocked in 1/2 clock period later with the falling clock edge. similarly, data in the r da/r db input is also clocked with the falling clock edge. the rtsa/rtsb output indicates, with a delay of one clock period, all bits that could be sent without a collision ( see 5.1 ). bus configuration, timing mode 2 this operating mode corresponds to bus configuration timing mode 1. however, in this case data are outputted on t da/t db with the falling clock edge and after one clock period evaluated on c da/c db. thus one full clock period is available during the output of data and their evaluation. transition on the rtsa/rtsb output also takes place with the falling clock edge. 3 transfer of data packets the configuration selected for the fifo controller is such that for worst case where messages are transmitted in a conditions non-optimized manner, a processor reaction time of more than 0.8 ms will result in messages. normally, the required reaction time is 1 ms. the 64 byte fifo has been designed as tandem fifo. in the case of short, successive messages, up to 2 messages can be stored. if long messages are transmitted and 32 bytes are stored in the rfifo, readout by the processor is prompted by interrupt. the processor must handle the interrupt request, before additionally 32 bytes are received via the serial interface (1 ms). after a remaining message of up to 16 bytes has been stored, it is possible to store the first 16 bytes of a new message. the internal memory is now full. the arrival of additional bytes will result in "data overflow", and a third new message in "frame overflow". the generated interrupts are inserted together with all additional information into a wait line to be individually forwarded to the processor. the information whether or not additional interrupts are present in the wait line can also be read out (bmr bit in star). after an interrupt has been processed, the hscc must be informed by the m c accordingly. note: the times listed are referenced to a data rate of 256 kbit/s. 3.1 receive direction additional information in addition to the message end interrupt, the following information is stored by the hscc in special registers: ?address combination and/or address field of the received frame ?the received frame? control field ?type of frame (command/response) ?crc result ?data in the rfifo yes/no ?"abort" with received frame yes/no ?data overflow ?length of message
sab 82520 saf 82520 semiconductor group 26 the message length can be read from an 8-bit register, whereby bits 0 ?4 indicate the number of bytes which are still stored in the fifo. bits 7 ?5 are ignored after counter status 7 has been reached, indicating in this case a message length exceeding 224 bytes. messages of less than 5 bytes (4 bytes with 1 byte address) between the start and the end flag are ignored in all modes except extended transparent mode 0. worst case reaction times when operating as lap-d controller, the following worst case reaction times can be expected in the frame receiving mode: one message, length 3 65 bytes reaction time equals 1 ms two messages, length 1 = 33, length 2 3 17 bytes reaction time equals 0.8 ms and/or 0.7 ms in the extended transparent mode three successive short frames reaction time equals 0.5 ms and/or 0.4 ms in the extended transparent mode note: length of message has been referenced to the length of the information field or, in the extended transparent mode, to the entire length between the start and the crc field. a data rate of 256 kbit/s has been assumed. example to illustrate operating mode of interrupt wait line the example illustrates the arrival of four successive frames. additional information with respect to the interrupt/command bits has been included under chapter 6.1 subsequent to the arrival of the 32 bytes, the hscc generates the "receive pool full" interrupt (rpf) no reaction by the m c since the m c does not acknowledge this interrupt, the remaining message as well as the subsequent message are stored in the internal message memory. since the internal message memory is now full, the next s frame is lost and a "frame overflow" interrupt is generated. after the m c acknowledges the first interrupt, the next frame can be received and inserted into the wait line. figure 15 interactions m c hscc with continuous reception of messages
sab 82520 saf 82520 semiconductor group 27 3.2 transmit direction again 2 32 byte buffers have been provided in the transmit direction. after writing up to 32 bytes into the xfifo, the hscc can be prompted by command to transmit. two different types of frames can be transmitted. for i frames the address and control field are generated autonomously by the hscc and the data in the xfifo are entered into the information field. for transparent frames, the address and control fields must be entered in the xfifo as well. if the transmit request does not include an end flag, the hscc will request the next data packet by interrupt, if not more than 32 bytes are stored in the xfifo. this process will be repeated until the m c indicates by command the end of the message. in the case where no more data are available in the xfifo prior to the arrival of the end of message indication, the transmitted message is aborted and the m c is informed accordingly by interrupt (xdu). it is possible to abort a message by software (xres). when suitably programmed, the hscc will perform a bus access control autonomously. collisions which occur up to the 32nd data byte can be treated by the hscc without interaction. if a collision is detected after the 32nd data byte, the hscc terminates the message and prompts the processor to repeat the message (xmr). an interrupt (xpr) will also be generated after a transparent frame has been transmitted in full. in addition, the "ready to write/not ready to write" status of the xfifo can be read from star at any time. 4 procedural support in addition to address recognition, the hscc autonomously processes all s and i frames (prerequisite window size 1) in the auto mode. the following functions will be performed: updating of transmit and receive counter evaluation of transmit and receive counter processing of s commands flow control with rr/rnr generation of responses recognition of protocol errors transmitting of s commands, if acknowledgement is missing continuous status query of opposite termination after rnr has been received programmable timer/repeater functions in addition, all u frames are forwarded directly to the processor. additional logic connections can be operated in parallel by software. the logic link can be initialized by software at any time (rhr).
sab 82520 saf 82520 semiconductor group 28 4.1 reception of frames the logic processing of received s frames is performed by the hscc without interrupting the m c. the m c is merely informed by interrupt with respect to status changes in the opposite termination (receive ready/not receive ready) and protocol errors (unacceptable n (r) or s frame with i field). i frames are also processed autonomously and checked for protocol errors. the i frame will not be accepted in the case of sequence errors (no interrupt is forwarded to the m c), but is immediately confirmed by an s response. if the m c sets the hscc into a "receive not ready" status, an i frame will not be accepted (no interrupt) and an rnr response is transmitted. u frames are always stored in the r fifo and forwarded directly to the m c. the logic sequence and the reception of a frame in the auto mode is illustrated in figure 16 . 4.2 transmission of frames the hscc autonomously transmits s commands and s responses in the auto mode. either transparent or i frames can be transmitted by the user. the software timer has to be operated in the internal timer mode to transmit i frames. after the frame has been transmitted, the timer is self-started, the x fifo is inhibited, and the hscc, waits for the arrival of a positive acknowledgement. this acknowledgement can be provided by means of an s or i frame. if no positive acknowledgement is received during time t 1, the hscc transmits an s command (p = 1), which must be followed by an s response (f = 1). if the s response is omitted, the process is performed n1 times, before it is terminated. upon the arrival of an acknowledgement or after the completion of this poll procedure, the xfifo is enabled and an interrupt is forwarded to the m c. interrupts may be triggered by the following: message has been acknowledged as positive (xpr interrupt) message must be repeated (xmr interrupt) response has not been received (tin interrupt) upon arrival of an rnr frame, the software timer is started and the status of the opposite termination is queried periodically after expiration of t 1 , until the status "receive ready" has been detected. the user is informed accordingly via interrupt. also, after the n1th absence of a response, an interrupt will be generated (tin interrupt). as a result, the process will be terminated as illustrated in figure 17 . note: the internal timer mode should only be used in the auto mode. transparent frames can be transmitted in all operating modes. after the transmission of a transparent frame, the xfifo is immediately enabled, which is confirmed by interrupt (xpr). in this case, time monitoring can be performed with the timer in the external timer mode. 4.3 examples of interaction between the hscc and the m c the interaction between the hscc and the m c during the transmission and reception of i frames is illustrated in figure 18 the flow control with rr/rnr during the reception of i frames in figure 19 and during the transmission of i frames in figure 20 . both the sequence of the poll cycle and protocol errors are illustrated in figure 21 . the definition of the interrupt/command bits is contained under chapter 6.
semiconductor group 29 sab 82520 saf 82520 figure 16 logical processing of received frames in auto mode
semiconductor group 30 sab 82520 saf 82520 figure 17 timer procedure/poll cycle
semiconductor group 31 sab 82520 saf 82520 figure 18 transmission/reception i frames
semiconductor group 32 sab 82520 saf 82520 figure 19 flow control with rr/rnr: receiving i frame
semiconductor group 33 sab 82520 saf 82520 figure 20
semiconductor group 34 sab 82520 saf 82520 5 special functions 5.1 bus operation the balanced procedure with lapd in a point-to-multipoint configuration is effectively supported by the bus implemented in the hscc. the component autonomously performs a bus access procedure with collision detection and rotating priorities. as a result, any number of transmitters can be connected to the serial bus configuration. figure 22 bus configuration, point-to-multipoint additionally, in the bus mode, "multimaster" configuration can be realized, which implies the possibility of communication between any two stations. this communication is autonomously controlled by the hscc. figure 23 bus configuration, multimaster prerequisites for bus operation ?central clock supply for all transmitters ?nrz encoding ?or connection of data at the bus ?feedback of bus information (ctsa /cutsb input)
semiconductor group 35 sab 82520 saf 82520 the rtsa/rtsb output will in this case be active only when a frame is being transmitted. the signal is delayed by one clock period with respect to the data output txda/txdb, and marks all data bits that could be transmitted without collision. in this way a configuration may be implemented in which the bus access is resolved on a local basis (collision bus) and where the data are sent one clock period later on a separate transmission line. figure 24 request-to-send in bus operation note: the bus mode can be operated independently of the clock mode, e.g. also during clock mode 1 (receive and transmission strobe) or clock mode 5 (programmable time slots). bus access procedure the idle state of the bus is identified by eight or more successive 1?. in case of a transmit request in the hscc, the frame is transmitted and the bus is identified as busy with the first zero of the opening flag (start flag). after the frame has been transmitted, the bus becomes available again by transmitting 1?. note: if the bus is occupied by other transmitters and/or there is no transmit request in the hscc, log 1 will be continuously transmitted at the txda/txdb output. collisions during the transmitting process, the data transmitted from the hscc is compared with the data on the bus. in case an erroneous bit is detected (log 1 sent and log 0 detected, or vice versa) the frame is immediately aborted, and idle (log 1) is transmitted. transmission will be initiated again by the hscc as soon as possible. since a transmitted zero is given priority over a 1 due to the or connection at the bus, and since the individually combined stations in the address field of the transmitted hdlc frame differ from one another, the fact that a collision has occurred will be detected prior to or at the latest within the address field. the frame of the transmitter with the highest temporary priority (address field) is not affected and is transmitted without interruptions. all other transmitters terminate their operation immediately. note: if a wired or connection has been realized by an external pull-up resistor without decoupling, the data output (txda/txdb) can be used as an open drain output and connected directly to the ctsa /ctsb output.
semiconductor group 36 sab 82520 saf 82520 figure 25 synchronization of the data clock in dpll mode
semiconductor group 37 sab 82520 saf 82520 priority principle when an hdlc frame has been successfully transmitted by the hscc, the priority is decremented. in order to transmit an additional frame, ten successive 1? must be present on the bus. this fact is used as a criterion to ensure that the higher priority transmitters do not contain any transmit requests. it is now possible to transmit a frame and the priority can be increased again (8 successive 1?). this method offers a priority allocation based on the selection of a particular address. it also ensures that each subscriber can access the bus at a pre-determinable time. 5.2 baud rate generation the internal baud rate generator adjusts the oscillator frequency in an external high-frequency clock to the reference clock required by the dpll?. the required frequency ratio can be programmed as one of the following: 1, 2, 4, 6 . . . 2048, using the baud rate generator register (bgr) and the timing control register (tcr). 5.3 dpll mode the dpll circuits implemented in the hscc are optimized with respect to the hdlc protocol. the data clock is equal to the reference clock when divided by 16, the phase of the reference clock being synchronized to the received data stream. when using the nrzi encoding, the zero insert/zero delete method ensures that a sufficient number of edges occur in the data stream during the reception of an hdlc frame. the following functions have been implemented to faciliate a high-speed and reliable synchronization ( see figure 25 ). ?interference rejection in the case where two or more edges appear in the data stream within a time period of 16 reference clocks, these are detected as interference without performing additional adjustments. ?phase adjustment in the case where an edge with a phase angle of 20? semiconductor group 38 sab 82520 saf 82520 6 detailed register description the parameterization of the hscc as well as the transfer of data and control information between the m c and the hscc is performed for each channel with two fifo? (rfifo, xfifo) and a set of registers. the addresses 00 h ?f h and 40 h ?5f have been reserved for accessing fifo?. the addresses in this range are of equal value and refer to the current byte in the fifo. as a result, performance oriented move string commands can be applied. all hscc registers may be accessed via even or odd cpu addresses, thus enabling a direct connection to the upper or lower half of a 16 bit microprocessor address/data bus. 6.1 register set hdlc controller register addresses 40 ?5f 00 ?1f rfifo xfifo 30, b1 20, a1 ista mask 31, b0 21, a0 star cmdr 32, b3 22, a3 mode mode 33, b2 23, a2 timr timr 34, b5 24, a5 exir xad1 35, b4 25, a4 rfbc xad2 36, b7 26, a7 rah1 37, b6 27, a6 rsta rah2 38, b9 28, a9 ral1 ral1 39, b8 29, a8 rhcr ral2 channel b channel a addr h read write refer to page 38 39/40 41 42 39 42 44 43/44 44 45
semiconductor group 39 sab 82520 saf 82520 control registers interrupt status register (ista) read ?address 20/30 value after reset: 00 h 7 0 exb exa ica tin xpr rsc rpf rme rme receive message end; one complete message 32 bytes or the last part of message > 32 bytes are in the receive fifo. rpf receive pool full; 32 bytes of a message are entered in the receive fifo; message has not yet been completed. rsc receive status change; change in status (receive ready/receive not ready) with respect to the opposite terminator was detected in the auto mode. current status can be read from star (rrnr bit). xpr transmit pool ready; one data block can be entered into the x-fifo. tin timer interrupt; expiration of timer and repeat counter. ica interrupt of channel a; refers to the interrupt status register (ista) of channel a. exa extended interrupt of channel a; refers to the extended interrupt register (exir) of channel a. exb extended interrupt of channel b; refers to the extended interrupt register (exir) of channel b. mask register (mask) write ?address 20/30 after the respective register has been read, ica, exa and exb are deleted. all other bits are deleted after reading ista. to prevent erroneous functions, each bit is individually monitored and reset. note: bit 2-0 is only used in ista/channel b. value after reset: 00 h each interrupt source can be selectively masked by setting the respective bit in mask. masked interrupts are not indicated when reading ista. instead, they remain internally stored and will be indicated after the masking process has been terminated. note: in the event of an extended interrupt, no interrupt will be generated with a masked exi bit, instead this bit is set in ista.
semiconductor group 40 sab 82520 saf 82520 extended interrupt register (exir) read ?address 24/34 value after reset: 00 h 7 0 0 0 0 csc rfo pce xdu xmr xmr transmit message repeat; message has to be repeated due to negative acknowledgement (auto mode) or collision detected after the 32nd data byte. xdu transmit data underrun; transmitted frame was terminated with "idle". no additional data in the xfifo. note: it is not possible to transmit transparent frames or i frames when an xmr or xdu interrupt is set. pce protocol error; indication of a protocol error in the auto mode. either an s or i frame with an incorrect n (r), or an s frame with i field has been received. rfo receive frame overflow; frame could not be stored due to occupied internal message buffer. csc clear-to-send change; if cie bit is set (tcr) this bit indicates a change on cts input. the actual value can be read from star. status register (star) read ?address 21/31 value after reset: 48 h 7 0 0 cts cec mbr rrnr xrnr xfw xdov xdov transmit data overflow; more than 32 bytes have been written into the xfifo. xfw xfifo write enable; data can be entered into the x fifo. xrnr transmit rnr; indication of the status of the hscc in the auto mode. rrnr received rnr; indication of the status of the remote station. mbr message buffer ready; at least one more frame can be stored in the rfifo. cts clear to send; if cie bit is set (tcr) this bit indicates the state of the cts input (inverted). cec command execution control; this bit is set during the time a command, written in cmdr, is executed.
semiconductor group 41 sab 82520 saf 82520 command register (cmdr) write ?address 21/31 value after reset: 00 h 7 0 xres xme xif xtf sti rnr rhr rmc rmc receive message complete; reaction to rpf or rme interrupt. current frame or data block was fetched by m c and can be deleted. rhr reset hdlc receiver; hdlc receiver is reset. all data as well as the content of the message buffers are deleted. in the auto mode, the transmit and receive counters are reset as well. rnr receive not ready; status of the icc is set to "receive not ready" (log 1) and/or "receive ready" (log 0) (auto mode). sti start timer; software timer is started. xtf transmit transparent frame; transmission of a transparent frame is initiated. xif transmit i frame; transmission of an i frame is initiated. xme transmit message end; last part of frame was entered in x fifo. xres transmit reset; hdlc transmitter is reset, xfifo is deleted and idle is transmitted. note: execution of a command written in cmdr takes at most two and a half transmit clock periods. during this time cec (star) is set and cmdr must not be written again.
semiconductor group 42 sab 82520 saf 82520 mode register (mode) r/w ?address 22/32 value after reset: 00 h 7 0 tlp trs rts rac tmd adm mds0 mds1 mds1-0 mode select; operating mode of hdlc controller is selected. 00 auto mode 01 non-auto mode 10 transparent mode 11 extended transparent mode adm address mode; one byte address field (log 0) or two byte address field (log 1) of the hdlc frame. differentiation between extended transparent mode 0 and extended transparent mode 1 in the extended transparent mode. rac receiver active; receiver is activated (log 1) or deactivated (log 0). tmd timer mode; operating mode of the software timer is set. internal mode (log 1) or external mode (log 0). rts request to send; rts output is activated (log 1) or is autonomously controlled by the hscc (log 0). trs timer resolution select; resolution of sw timer (factor k ) is set to 2 15 (log 0) and/or 2 9 (log 1) clock periods. tlp test loop; input and output of hdlc channel are connected.
semiconductor group 43 sab 82520 saf 82520 time register (timr) r/w ?address 23/33 7 0 e u l a v t n c value time period is set. the time period is t 1 = k (value + 1) + tcp factor k can be set for 2 15 or 2 9 clock periods in mode, tcp is the clock period of transmit data. cnt count; interpreted in accordance with the selected operating mode. internal timer mode: cnt indicates the number of s commands (max. 6); in the case where an i frame is not acknowledged, these are autonomously transmitted by the hscc after the expiration of time t 1 . cnt = 7 indicates an unlimited number of s commands. external timer mode: cnt plus value indicates the time period t 2 after which the timer interrupt will be generated. the time period t 2 is: t 2 = 32 k cnt tcp + t 1 when cnt = 7, a timer interrupt is regularly generated after the expiration of t 1 . note: writing timr stops the timer, regardless of the timer mode. receive frame byte counter (rfbc) read ?address 25/35 value after reset: 00 h 7 0 rdc0 rdc7 rdc7-0 receive data count: message length of received frame. rdc4-0 always indicates the length of data block available in the receive fifo. when the messages exceed 223 bytes rdc7-5 is held at the value 7.
semiconductor group 44 sab 82520 saf 82520 receive status register (rsta) read ?address 27/37 7 0 la c/r ha0 ha1 rab crc rdo rda rda data received; data are available in the receive fifo rdo receive data overflow; data overflow with current frame crc crc compare; positive crc comparison rab receive message aborted; received frame was aborted ha1, ha0 high byte address compare; identifier for address identification 10 rah1 00 rah2 01 group address (fe or fc) note: if the identical value is entered into rah1 and rah2, the combination 00 will be omitted. c/r command-response; value of the c/r bit in the received frame. la low byte address compare; ral1 (log1) or ral2 (log 0) values have been recognized. note: in the transparent and extended transparent mode bit 0 is irrelevant; when amd = 0 (mode) bits 1? are irrelevant. data register receive fifo (rfifo) read ?address 0/40 the received data can be read from the r fifo after an rme or rpf interrupt. transmit fifo (xfifo) write ?address 0/40 data to be transmitted can be written into the x fifo after an xpr interrupt. transmit address 1 (xad1) write ?address 24/34 high address byte high of lap processed in the auto mode. xad1 will be interpreted as command in the one byte address mode. note: in the two byte address mode bit 1 must be set to log 0. transmit address 2 (xad2) write ?address 25/35 low address byte low of lap processed in the auto mode. xad2 will be interpreted as command in the one byte address mode. note: in the two byte address mode bit 1 must be set to log 0.
semiconductor group 45 sab 82520 saf 82520 receive address byte high register (rah1) write ?address 26/36 7 0 0 cri 1 h a r rah1 value of the first individual address, higher byte. cri command-response bit interpretation: in the case of a two byte address in auto mode the c/r bit will be handled as follows: commands rec 0 1 responses rec 1 0 commands trm 1 0 responses trm 0 1 cri = 1 c/r value cri = 0 c/r value receive address byte high register (rah2) write ?address 27/37 7 0 0 mcs 2 h a r note: in the case of a one-byte address rah1 must be set to 00 h . rah2 value of the second individual address, higher byte. mcs modulo count select (valid in auto mode only). the mcs bit determines the control field format according to hdlc 0: basic operation (modulo 8) 1: extended operation (modulo 128) receive address byte low register (ral 1) r/w ?address 28/38 value of the first address lower byte (auto, non-auto mode); in the case of a one byte address, interpreted as command. the received lower byte address (transparent mode), the first byte after the flag (extended transparent mode 1), or a data byte (extended transparent mode 1, with bypassing of the hdlc receiver) can be read out from this register. ral1 can be written in auto/non-auto mode and it can be read in other modes. receive address byte low register (ral 2) write ?address 29/39 value of the second individual address, lower byte (auto, non-auto mode), with a one byte address interpreted as response.
semiconductor group 46 sab 82520 saf 82520 receive hdlc control register (rhcr) read ?address 29/39 value of the received hdlc control field; in the transparent mode 0 value of the second byte after the flag. when modulo 128 is selected (mcs bit of rah2) in auto mode, the rhcr register contains compressed information of the extended control field, making it similar to a modulo 8 control field. bit 0 of the rhcr register has the following meaning: 0 ? an i -frame has been received 1 ? a u-frame has been received. (s-frames will be handled autonomously by the hscc). when message transfer modes other than the auto mode are used and a hdlc protocol is used with "modulo 128", then the first octet of the extended control field is available in the rhcr register. the second octet is available in the rfifo in accordance with to the message transfer mode. in extended transparent mode 0 (no address recognition) rhcr contains the second byte of a received frame after the opening flag.
semiconductor group 47 sab 82520 saf 82520 description of registers common configuration register (ccr) r/w ?address 2 f value after reset: 00 h 7 0 cm0 cm1 cm2 lss 0ds sc0 sc1 pu pu power up; switch-over between power-up and power-down mode. sc0 serial port configuration ( see page 23 ) sc1, 00 point-to-point configuration, nrz encoding 6.2 common register register addresses addr h read write 2b, aa bgr 2c, ad tcr tcr 2d, ac tsar 2e, ab tsax 2f, ae ccr ccr 10 point-to-point configuration, nrzi encoding 01 bus configuration, timing mode 1 11 bus configuration, timing mode 2 note: in the bus mode, only nrz encoding can be used. 0ds output driver select; the serial data outputs (t da, t db) are operated as push- pull (log 1) or open drain outputs (log 0). lss line sync select; in the idle state non shared zero flags (log 1) or idle (log 0) will be output at the serial data outputs. cm2-0 clocking mode; setting of the clock modes 0 ?7 ( see page 17 ).
semiconductor group 48 sab 82520 saf 82520 tsnr time-slot number receive; number of the receive time slot. tss time-slot select; 32 time slots in the frame (log 1) or 64 (log 0). tcs0 clock shift 0; setting of the clock shift in transmit direction, bit 0. time-slot assignment register transmit (tsax) write ?address 2 e 7 0 tcs1 tcs2 x n s t tsnx time-slot number transmit; number of the transmit time slot (00 h ?f h ) tcs2, tcs1 clock shift; setting of the clock shift in transmit direction, bit 2 and bit 1 ( see page 20 ). time-slot assignment register receive (tsar) write ?address 2 d 7 0 tcs0 tss r n s t
semiconductor group 49 sab 82520 saf 82520 timing control register (tcr) r/w ?address 2 c 7 0 0 0 cie ti0 ccs rcs0 rcs1 rcs2 value after reset: 00 h the effect of tcr depends on the clock mode. clock mode 5 7 0 0 0 cie ti0 tss bdf br8 br9 clock mode 2, 6 7 0 0 0 cie ti0 0 bdf br8 br9 clock mode 3, 4, 7 rcs 2-0 receive clock shift; timing shift of receive data ccs channel capacity select; 56 kbit (log 1) or 64 kbit channels (log 0) will be transmitted. 7 0 0 0 cie 0 0 0 0 0 clock mode 0, 1 note: the value of rcs2-0 must be set whenever a reset has been applied to the device. br9-8 baud rate, bit 9? bdf baud rate division factor; the division factor of the baud rate generator is one (log 0) or is adjusted by br9? (log 1). tss transmit clock source select; the source for the transmit clock is t clk a/ t clk b (log 0), or the baud rate generator output frequency divided by 16 (log 1). ti0 transmit clock input/output switch; t clk a/ t clk b pins are inputs (log 0) or output (log 1). note: in clock mode 5 only t clk b can be programmed as output. cie clear to send interrupt enable; csc interrupt (exir) is masked (log 0) or not (log 1). baud rate generator register (bgr) write ?address 2 b br7 br0 br7-0 baud rate, bit 7?; will determine, along with br9, br8, the division factor of the baud rate generator. supposing value n (0 1023) has been programmed, the division factor is k = 2 * ( n + 1).
semiconductor group 50 sab 82520 saf 82520 absolute maximum ratings limit values 7 electrical characteristics parameter symbol min. typ. max. unit test conditions limit values parameter symbol min. max. unit voltage at any pin vs. ground v s ?0.4 v cc + 0.4 v operating temperature: sab 82520 operating temperature: saf 82520 t a t a 0 ?40 70 85 ?c ?c storage temperature t stg ?65 125 ?c dc characteristics sab 82520 : t a = 0 to 70 ?c; v cc = 5 v 10 %; gnd = 0 v saf 82520 : t a = ?40 to 85 ?c; v cc = 5 v 5 %; gnd = 0 v l-input voltage h-input voltage v il v ih v cc ?.4 2.0 0.8 v cc +0. v v l-output voltage h-output voltage v ol v oh 2.4 v cc ?.5 v cc 0.45 v v v i ol = 2 ma i oh = ?400 m a i oh = ?100 m a input leakage current output leakage current i il i ol ?10 ?10 10 10 m a m a v in = v cc to 0 v v out = v cc to 0 v v cc supply current p. d. p. u. i cc i cc 0.5 5 1.8 7 ma ma v cc = 5 v c p = 4 mhz inputs at v ss / v cc no output loads capacitance t a = 25 ?c; v cc = gnd = 0 v parameter symbol min. typ. max. unit limit values input capacitance f c = 1 mhz c in 510pf input/output capacitance c i/o 10 20 pf output capacitance unmeasured pins returned to gnd c out 815pf
semiconductor group 51 sab 82520 saf 82520 figure 26 ac testing input, output waveform ac testing load circuit ac testing inputs are driven at 2.4 v for logic "1" and 0.45 v for logic "0". timing measurements are made at 2.0 v for logic "1" and at 0.8 v for logic "0".
semiconductor group 52 sab 82520 saf 82520 figure 27 m p interface timing read cycle read cycle limit values parameter symbol min. max. unit output float delay t df 25 ns data delay from rd rd pulse width t rd t rr 110 110 ns ns rd control interval t ri 60 ns address hold after ale address to ale setup t la t al 25 20 ns ns ale pulse width t aa 50 ns limit values parameter symbol min. max. unit write cycle wr pulse width data setup to wr t ww t dw 60 30 ns ns data hold after wr wr control interval t wd t wi 10 60 ns ns
semiconductor group 53 sab 82520 saf 82520 figure 28 serial interface timing dc characteristics sab 82520 : t a = 0 to 70 ?c; v cc = 5 v 10 %; gnd = 0 v saf 82520 : t a = ?40 to 85 ?c; v cc = 5 v 5 %; gnd = 0 v limit values parameter symbol min. max. unit transmit data delay t xdd 20 68 ns collision data setup collision data hold t cds t cdh 0 30 ns ns receive data setup receive data hold t rds t rdh 0 30 ns ns request to send delay 1 request to send delay 2 t rtd 1 t rtd 2 30 20 130 85 ns ns clock period t cp 240 ns clock period low clock period high t cpl t cph 90 100 ns ns
semiconductor group 54 sab 82520 saf 82520 figure 29 clock mode 5 limit values parameter symbol min. max. unit sync pulse delay t sd 30 ns time-slot control 2 delay time-slot control 1 delay t tcd 2 t rcd 1 20 30 95 120 ns ns sync pulse setup t ss 30 ns sync pulse width t sw 40 ns
semiconductor group 55 sab 82520 saf 82520 figure 30 clock mode 1 limit values parameter symbol min. max. unit receive strobe delay receive strobe setup receive strobe hold t rsd t rss t rsh 30 70 30 ns ns ns transmit strobe delay transmit strobe setup transmit strobe hold t xsd t xss t xsh 30 90 30 ns ns ns
semiconductor group 56 sab 82520 saf 82520 clock mode 2, 3, 6, 7 limit values parameter symbol min. max. unit clock frequency baudrate generator used f clk 12.3 mhz internal clocking clock frequency baudrate generator not used f clk 19.3 mhz reset timing res characteristics limit values parameter symbol min. max. unit res high t rwh 1800 ns
semiconductor group 57 sab 82520 saf 82520 8 package outlines plastic package, p-dip-28 (dual-in-line) gpd05037 plastic package, p-lcc-28-r (smd) (plastic-leaded chip carrier) gpl05018 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information dimensions in mm

▲Up To Search▲

Price & Availability of SAF82520-N

	To Download SAF82520-N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .